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| 型号： | MC68HC901FNR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封装： | PLASTIC, LCC-52 |
| 文件页数： | 43/73页 |
| 文件大小： | 274K |
| 代理商： | MC68HC901FNR2 |
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Universal Synchronous/Asynchronous Receiver-Transmitter
7-5
MC68HC901 USER’S MANUAL
MOTOROLA
the RSR was read to access the status information for the first data word, the flags for the
new word would be retrieved.
7.2.1 Receiver Interrupt Channels
The USART receiver section is assigned two interrupt channels. One indicates the buffer full
condition while the other channel indicates an error condition. Error conditions include
overrun, parity error, frame error, synchronous found, and break. These interrupting
conditions correspond to the OE, PE, FE, and F/S or B bits of the receiver status register.
These flags will function as described in Section 7.2.2 Receiver Status Register whether
the receiver interrupt channels are enabled or disabled.
While only one interrupt is generated per character received, two dedicated interrupt
channels allow separate vector numbers to be assigned for normal and abnormal receiver
conditions. When a received word has an error associated with it and the error interrupt
channel is enabled, an interrupt will be generated on the error channel only. However, if the
error channel is disabled, an interrupt for an error condition will be generated on the buffer
full interrupt channel along with interrupts produced by the buffer full condition. The receiver
status register must always be read to determine which error condition produced the
interrupt.
7.2.2 Receiver Status Register (RSR)
The RSR contains the receiver buffer full flag, the synchronous strip enable, the various
status information associated with the data word in the receive buffer. The RSR is latched
each time a data word is transferred to the receive buffer. RSR flags cannot change again
until the new data word has been read. However, the M/CIP bit is allowed to change.
BF— Buffer Full
Receiver word is transferred to the receive buffer. Receiver buffer is read by accessing the
USART data register.
1 = Receiver word transferred to buffer.
0 = Read by RSR.
OE— Overrun Error
Overrun error occurs when a received word is to be transferred to the receive buffer, but the
buffer is full. Neither the receiver buffer nor the RSR is overwritten. The OE bit is set after
the receive buffer full condition is satisfied by reading the UDR. This error condition will
generate an interrupt to the processor. The OE bit is cleared by reading the RSR. New data
words will not be assembled until the RSR is read.
RSR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
BF
OE
PE
FE
FS OR B
M OR CIP
SS
RE
RESET
0
ADDR
$2B
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