
Memory
Input/Output (I/O) Section
MC68HLC908QY/QT Family — Rev. 2
Data Sheet
MOTOROLA
Memory
27
$001C
Unimplemented
$001D
IRQ Status and Control
Register (INTSCR)
Read:
0000
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
00000000
$001E
Configuration Register 2
(CONFIG2)(1)
Read:
IRQPUD
IRQEN
R
OSCOPT1 OSCOPT0
R
RSTEN
Write:
Reset:
0000000
0(2)
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
$001F
Configuration Register 1
(CONFIG1)(1)
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVDLVR
SSREC
STOP
COPD
Write:
Reset:
0000
0(2)
000
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits.
2. LVDLVR reset to 0 by a power-on reset (POR) only.
$0020
TIM Status and Control
Register (TSC)
Read:
TOF
TOIE
TSTOP
00
PS2
PS1
PS0
Write:
0
TRST
Reset:
00100000
$0021
TIM Counter Register High
(TCNTH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
00000000
$0022
TIM Counter Register Low
(TCNTL)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
00000000
$0023
TIM Counter Modulo
Register High (TMODH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
11111111
$0024
TIM Counter Modulo
Register Low (TMODL)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
11111111
$0025
TIM Channel 0 Status and
Control Register (TSC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
$0026
TIM Channel 0
Register High (TCH0H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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