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| 型号： | MC68HRC705J5ACDWR3 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 38/106页 |
| 文件大小： | 1069K |
| 代理商： | MC68HRC705J5ACDWR3 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
RESETS
MOTOROLA
REV 2.1
5-3
The COPR will generate the RST signal which will reset the CPU and other
peripherals. Also, the COPR will establish the mode of operation based on the
state of the IRQ pin at the time the COPR signal ends. If the voltage on the IRQ
pin is at the VTST level, the state of the PB0 pin during the last rising edge of the
RESET pin will determine which Test Mode (Internal or Expanded) the MCU will
be in. If the voltage at the IRQ pin is in the normal operating range (VSS to VDD),
the MCU will enter Single-Chip Mode when the COPR signal ends. If any other
reset function is active at the end of the COPR reset signal, the RST signal will
remain in the reset condition until the other reset condition(s) end.
5.2.3 LOW VOLTAGE RESET (LVR)
The internal LVR reset is generated when VDD falls below the specied LVR trig-
ger value VLVR for at least one tCYC. In typical applications, the power supply de-
coupling circuit will eliminate negative-going voltage glitches of less than one
tCYC. This reset will hold the MCU in the reset state until VDD rises above VLVR.
Whenever VDD is above VLVR and below 4.5V, the MCU is guaranteed to operate
although not within specication. The output from the LVR is connected directly to
the internal reset circuitry and also forces the RESET pin low. The internal reset
will be removed once the power supply voltage rises above VLVR, at which time a
normal power-on-reset sequence occurs.
5.2.4 ILLEGAL ADDRESS RESET (ILADR)
The internal ILADR reset is generated when an instruction opcode fetch occurs
from an address which is not implemented in the RAM ($0080 - $00FF) nor ROM
($0300-$0CFF, $0E00-$0FFF). The ILADR will generate the RST signal which will
reset the CPU and other peripherals. If any other reset function is active at the end
of the ILADR reset signal, the RST signal will remain in the reset condition until
the other reset condition(s) end. Notice that ILADR also forces the RESET pin low.
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