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| 型号： | MC68HRC705J5ACDWR3 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 44/106页 |
| 文件大小： | 1069K |
| 代理商： | MC68HRC705J5ACDWR3 |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
LOW POWER MODES
MC68HC05J5A
6-4
REV 2.1
after a varied delay time which is from one to 224 or 4064 internal processor clock
cycles (the POR delay time). The HALT Mode is not intended for normal use, but
is provided to keep the COP Watchdog Timer active should the STOP instruction
opcode be inadvertently executed.
6.2
WAIT INSTRUCTION
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Internal timer clocks
remain active, permitting interrupts to be generated from the timer or a reset to be
generated from the COP Watchdog Timer. Execution of the WAIT instruction auto-
matically clears the I-bit in the Condition Code Register and sets the IRQE enable
bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their previous states.
If timer (MFT or Timer 1) interrupts are enabled, a TIMER interrupt will cause the
processor to exit the WAIT Mode and resume normal operation. The Timer may be
used to generate a periodic exit from the WAIT Mode. The WAIT Mode may also
be exited when an external IRQ or an LVR reset or an external RESET occurs.
6.3
DATA-RETENTION MODE
If the LVR mask option is selected and since LVR kicks in whenever VDD is below
the specied LVR trigger voltage which is higher than that required of the Data
Retention mode, the Data Retention mode will not exist. Data Retention Mode is
only meaningful if LVR mask option is not selected.
The contents of RAM and CPU registers are retained at supply voltage as low as
2.0 VDC. This is called the data-retention mode where the data is held, but the
device is not guaranteed to operate. The RESET pin must be held low during
data-retention mode.
6.4
COP WATCHDOG TIMER CONSIDERATIONS
The COP Watchdog Timer is active in all modes of operation if enabled by a mask
option. Thus, emulation of applications that do not service the COP should only be
done with devices that have the COP Mask Option disabled.
If the COP Watchdog Timer is selected by the mask option, any execution of the
STOP instruction (either intentional or inadvertent due to the CPU being dis-
turbed) will cause the oscillator to halt and prevent the COP Watchdog Timer from
timing out unless the STOP to HALT conversion feature is enabled. Therefore, it is
recommended that the STOP instruction should be converted to a HALT instruc-
tion if the COP Watchdog Timer is enabled.
If the COP Watchdog Timer is selected by the mask option, the COP will reset the
MCU when it times out. Therefore, it is recommended that the COP Watchdog
should be disabled for a system that must have intentional uses of the WAIT Mode
for periods longer than the COP time-out period.
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