参数资料
型号: MC68HSC05C8CP
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
封装: PLASTIC, DIP-40
文件页数: 16/116页
文件大小: 781K
代理商: MC68HSC05C8CP
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
112
Freescale Semiconductor
B.7 2.4-V to 3.6-V High-Speed SPI Timing
The data in 13.11 3.3-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the
exceptions given in the following table.
Num
Characteristic
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(1)
240
1. Signal production depends on software.
ns
3
Enable lag time
Master
Slave
tLag(M)
tLag(S)
(1)
720
ns
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
ns
6
Data setup time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
ns
7
Data hold time (Inputs)
Master
Slave
tH(M)
tH(S)
100
ns
8
Slave access time (time to data active from high-impedance state)
tA
0
120
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
240
ns
10
Data
Master (before capture edge)
Slave (after enable edge)(2)
2. Assumes 20 pF load on all SPI pins.
tV(M)
tV(S)
0.25
240
tCYC(M)
ns
11
Data Hold Time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
100
2.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
100
2.0
ns
s
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