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| 型号： | MC68HSC05C8CP |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 65/116页 |
| 文件大小： | 781K |
| 代理商： | MC68HSC05C8CP |
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Serial Communications Interface (SCI)
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
52
Freescale Semiconductor
9.4.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise.
Any conflict between noise-detection samples sets the noise flag (NF) in the SCSR. The NF bit is set at
the same time that the RDRF bit is set.
9.4.2.5 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error (FE) bit in the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.4.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1.
Receive data register full (RDRF) — The RDRF bit in the SCSR indicates that the receive shift
register has transferred a character to the SCDR.
2.
Receiver overrun (OR) — The OR bit in the SCSR indicates that the receive shift register shifted
in a new character before the previous character was read from the SCDR.
3.
Idle input (IDLE) — The IDLE bit in the SCSR indicates that 10 or 11 consecutive logic 1s shifted
in from the PD0/RDI pin.
9.5 SCI Input/Output (I/O) Registers
These I/O registers control and monitor SCI operation:
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
9.5.1 SCI Data Register
The SCI data register is the buffer for characters received and for characters transmitted.
Address:
$0011
Bit 7
654321
Bit 0
Read:
SCD7
SDC5
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Write:
Reset:
Unaffected by reset
Figure 9-4. SCI Data Register (SCDR)
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