Bus Control and Input/Output (I/O)
MC68HC812A4 Data Sheet, Rev. 7
64
Freescale Semiconductor
Port D and its associated data direction register may be removed from the on-chip map when port D is
needed for 16-bit data transfers. If the MCU is in an expanded wide mode, port C and port D are used for
16-bit data and the associated port and data direction registers become external accesses. When the
MCU is in expanded narrow mode, the external data bus is normally 8 bits. To allow full-speed operation
while allowing visibility of internal 16-bit accesses, a 16-bit-wide data path is required. The emulate port
D (EMD) control bit in the MODE register may be set to allow such 16-bit transfers. In this case of narrow
special expanded mode and the EMD bit set, port D and data direction D registers are removed from the
on-chip memory map and become external accesses so port D may be rebuilt externally.
In any expanded mode, port E pins may be needed for bus control (for instance, ECLK and R/W). To
regain the single-chip functions of port E, the emulate port E (EME) control bit in the MODE register may
be set. In this special case of expanded mode and EME set, PORTE and DDRE registers are removed
from the on-chip memory map and become external accesses so port E may be rebuilt externally.
6.3.1 Port A Data Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
Bits PA7–PA0 are associated with addresses ADDR15–ADDR8 respectively. When this port is not used
for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O.
DDRA determines the primary direction of each pin. This register is not in the on-chip map in expanded
and peripheral modes.
6.3.2 Port A Data Direction Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
This register determines the primary direction for each port A pin when functioning as a general-purpose
I/O port. DDRA is not in the on-chip map in expanded and peripheral modes.
1 = Associated pin is an output.
0 = Associated pin is a high-impedance input.
Address: $0000
Bit 7
6
5432
1
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
00
0000
00
Expanded and peripheral:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
Figure 6-1. Port A Data Register (PORTA)
Address: $0002
Bit 7
654321
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
Figure 6-2. Port A Data Direction Register (DDRA)