Serial Communications Interface Module (SCI)
MC68HC812A4 Data Sheet, Rev. 7
172
Freescale Semiconductor
SBK — Send Break Bit
Toggling SBK sends one break character (10 or 11 logic 0s). As long as SBK is set, the transmitter
sends logic 0s.
1 = Transmit break characters
0 = No break characters
14.6.4 SCI Status Register 1
Read: Anytime
Write: Has no meaning or effect
TDRE — Transmit Data Register Empty Flag
TDRE is set when the transmit shift register receives a byte from the SCI data register. Clear TDRE
by reading SCI status register 1 with TDRE set and then writing to the low byte of the SCI data register.
1 = Transmit data register empty
0 = Transmit date register not empty
TC — Transmission Complete Flag
TC is set when the TDRE flag is set and no data, preamble, or break character is being transmitted.
When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 with TC
set and then writing to the low byte of the SCI data register. TC clears automatically when a break,
preamble, or data is queued and ready to be sent.
1 = Transmission complete
0 = Transmission in progress
RDRF — Receive Data Register Full Flag
RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF
by reading SCI status register 1 with RDRF set and then reading the low byte of the SCI data register.
1 = Receive data register full
0 = Data not available in SCI data register
IDLE — Idle Line Flag
IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the
receiver input. Clear IDLE by reading SCI status register 1 with IDLE set and then writing to the low
byte of the SCI data register. Once IDLE is cleared, a valid frame must again set the RDRF flag before
an idle condition can set the IDLE flag.
1 = Receiver input has become idle
0 = Receiver input is either active now or has never become active since the IDLE flag was last
cleared
NOTE
When the receiver wakeup bit (RWU) is set, an idle line condition does not
set the IDLE flag.
SCI0: $00C4
SCI1: $00CC
Bit 7
6
5
4321
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
Write:
Reset:
110
00000
= Unimplemented
Figure 14-21. SCI Status Register 1 (SC0SR1 or SC1SR1)