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型号： MC8640DTVU1000NC
厂商： Freescale Semiconductor
文件页数： 52/130页
文件大小： 0K
描述： MPU DUAL E600 994-FCCBGA
标准包装： 1
系列： MPC86xx
处理器类型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
电压： 0.95V
安装类型： 表面贴装
封装/外壳： 994-BCBGA，FCCBGA
供应商设备封装： 994-FCCBGA（33x33）
包装： 托盘
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
28
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information, see
Section 18.4.2, “Platform to FIFO Restrictions.”
NOTE
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
A summary of the FIFO AC specifications appears in Table 26 and Table 27.
Table 26. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period (GMII mode)
tFIT
8.4
8.0
100
ns
TX_CLK, GTX_CLK clock period (Encoded mode)
tFIT
6.4
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH/tFIT
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
—
250
ps
Rise time TX_CLK (20%–80%)
tFITR
—
0.75
ns
Fall time TX_CLK (80%–20%)
tFITF
—
0.75
ns
FIFO data TXD[7:0], TX_ER, TX_EN setup time to
GTX_CLK
tFITDV
2.0
—
ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold
time
tFITDX
0.5
—
3.0
ns
Table 27. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
RX_CLK clock period (GMII mode)
tFIR
1
8.4
8.0
100
ns
RX_CLK clock period (Encoded mode)
tFIR
1
6.4
8.0
100
ns
RX_CLK duty cycle
tFIRH/tFIR
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
—
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
—
0.75
ns
Fall time RX_CLK (80%–20%)
tFIRF
—
0.75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
—
ns
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