参数资料
型号: MC8641DTVU1333JE
厂商: Freescale Semiconductor
文件页数: 94/130页
文件大小: 0K
描述: IC MPU DUAL CORE E600 1023FCCBGA
标准包装: 1
系列: MPC86xx
处理器类型: 32-位 MPC86xx PowerPC
速度: 1.333GHz
电压: 1.05V
安装类型: 表面贴装
封装/外壳: 1023-BCBGA,FCCBGA
供应商设备封装: 1023-FCCBGA(33x33)
包装: 托盘
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
66
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
MPC8641D SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45
assumes that the LVPECL clock driver’s output impedance is 50
Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140
Ω to 240 Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8641D SerDes
reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential
peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference
clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25
Ω.
Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with
a particular clock driver chip.
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK
Driver Chip
R2
R1
MPC8641D
R1
10nF
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