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参数资料
| 型号： | MC88LV915TFN |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 10/11页 |
| 文件大小： | 459K |
| 代理商： | MC88LV915TFN |
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MOTOROLA
Figure 3. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T
47
BOARD VCC
0.1F (LOOP
FILTER CAP)
330
1M
0.1F HIGH
FREQ
BYPASS
10F LOW
FREQ BYPASS
47
BOARD GND
8
9
10
ANALOG VCC
RC1
ANALOG GND
ANALOG LOOP FILTER/VCO
SECTION
OF
THE
MC88LV915T 28-PIN PLCC
PACKAGE (NOT DRAWN TO
SCALE)
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULDNOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88LV915T IN A NORMAL
DIGITAL ENVIRONMENT.
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 3 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1b.The 47
resistors, the 10F low frequency bypass
capacitor, and the 0.1
F high frequency bypass capacitor
form a wide bandwidth filter that will minimize the
88LV915T’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This filter will
typically ensure that a 100mV step deviation on the digital
VCC supply will cause no more than a 100pS phase
deviation on the 88LV915T outputs. A 250mV step
deviation on VCC using the recommended filter values
should cause no more than a 250pS phase deviation; if a
25
F bypass capacitor is used (instead of 10F) a 250mV
VCC step should cause no more than a 100pS phase
deviation.
If good bypass techniques are used on a board design
near components which may cause digital VCC and ground
noise, the above described VCC step deviations should not
occur at the 88LV915T’s digital VCC supply. The purpose
of the bypass filtering scheme shown in Figure 3 is to give
the 88LV915T additional protection from the power supply
and ground plane transients that can occur in a high
frequency, high speed digital system.
1c.There are no special requirements set forth for the loop
filter resistors (1M
and 330). The loop filter capacitor
(0.1
F) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3
A). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5M
reference
resistor should be used (instead of 1M
).
2. In addition to the bypass capacitors used in the analog filter
of Figure 3, there should be a 0.1
F bypass capacitor
between each of the other (digital) four VCC pins and the
board ground plane. This will reduce output switching
noise caused by the 88LV915T outputs, in addition to
reducing potential for noise in the ‘analog’ section of the
chip. These bypass capacitors should also be tied as close
to the 88LV915T package as possible.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88LV915T
Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
NETCOM
IDT Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV915T
8
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