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参数资料
| 型号： | MC88LV915TFN |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 9/11页 |
| 文件大小： | 459K |
| 代理商： | MC88LV915TFN |
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MOTOROLA
Figure 2c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back
Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back
Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back
Q4
Q5
Allowable Input Frequency Range:
20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
Allowable Input Frequency Range:
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)
In this application, the 2X_Q output is connected
to the FEEDBACK input. The internal PLL will line
up the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/4 the 2X_Q fre
quency, and the Q" outputs will run at 1/2 the
2X_Q frequency.
2:1 Input to Q" Output Frequency Relationship
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the Q" outputs) will
equal the SYNC frequency. The Q/2 output will al
ways run at 1/2 the Q" frequency, and the 2X_Q
output will run at 2X the Q" frequency.
1:1 Input to Q" Output Frequency Relationship
Allowable Input Frequency Range:
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q"
outputs (Q0-Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
1:2 Input to Q" Output Frequency Relationship
50MHz FEEDBACK SIGNAL
25MHz FEEDBACK SIGNAL
25MHz
SIGNAL
25MHz
SIGNAL
100MHz FEEDBACK SIGNAL
2X_Q
ANALOG VCC
CRYSTAL
OSCILLATOR
100MHz INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
Q/2
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
RC1
MC88LV915T
EXTERNAL
LOOP
FILTER
100MHz SIGNAL
2X_Q
ANALOG VCC
CRYSTAL
OSCILLATOR
50MHZ INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
Q/2
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
RC1
MC88LV915T
EXTERNAL
LOOP
FILTER
100MHz SIGNAL
2X_Q
ANALOG VCC
50MHz
Q"
CLOCK
OUTPUTS
CRYSTAL
OSCILLATOR
25MHz INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
Q/2
Q4
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
RC1
MC88LV915T
Q5
EXTERNAL
LOOP
FILTER
50MHz
Q"
CLOCK
OUTPUTS
50MHz
Q"
CLOCK
OUTPUTS
Note: If the OE/RST input is active, a pull-up or pull-down re
sistor isn't necessary at the FEEDBACK pin so it won't when
the fed back output goes into 3-state.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88LV915T
Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
NETCOM
IDT Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV915T
7
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