参数资料
型号: MC9328MX1DVM20R2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封装: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件页数: 17/94页
文件大小: 1487K
代理商: MC9328MX1DVM20R2
24
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.8.2.2 DTACK Read Cycle DMA Enabled
Figure 7. DTACK Read Cycle DMA Enabled
7
Data ready after DTACK asserted
0
T
ns
8
OE negated to CS negated
0.5T+0.24
0.5T+0.67
ns
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
ns
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
RW
DTACK
Address
EB
CS5
OE
(logic high)
Databus
programmable
min 0ns
(1)
(6)
(7)
(3)
(4)
(2)
(5)
(8)
(input to MX1)
(9)
(10)
(11)
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