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参数资料
| 型号： | MC9328MX1VM20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 200 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256 |
| 文件页数： | 77/94页 |
| 文件大小： | 1487K |
| 代理商： | MC9328MX1VM20 |
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Specifications
MOTOROLA
MC9328MX1 Advance Information
79
3.19 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 63. Definition of Bus Timing for I2C
3.20 Synchronous Serial Interface
The MC9328MX1 processor contains two identical SSI modules. The transmit and receive sections of the
SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a
common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each
have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected.
In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during
transmission. The internal and external clock timing diagrams are shown in Figure 65 through Figure 67
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
Table 39. I2C Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
Hold time (repeated) START condition
182
–
160
–
ns
2
Data hold time
01710150
ns
3
Data setup time
11.4
–
10
–
ns
4
HIGH period of the SCL clock
80
–
120
–
ns
5
LOW period of the SCL clock
480
–
320
–
ns
6
Setup time for STOP condition
182.4
–
160
–
ns
SDA
SCL
1
2
3
4
6
5
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相关代理商/技术参数 |
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| MC9328MX1VM20R2 | 功能描述:处理器 - 专门应用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21_06 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21_09 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21_10 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:266 MHz i.MX family of microprocessors |
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