参数资料
型号: MC9328MX1VM20
厂商: Freescale Semiconductor
文件页数: 99/100页
文件大小: 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
标准包装: 152
系列: i.MX1
核心处理器: ARM9
芯体尺寸: 32-位
速度: 200MHz
连通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 110
程序存储器类型: ROMless
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 256-MAPBGA
包装: 托盘
Product Documentation
MC9328MX1 Technical Data, Rev. 7
98
Freescale Semiconductor
6
Product Documentation
6.1
Revision History
Table 45 provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.
6.2
Reference Documents
The following documents are required for a complete description of the MC9328MX1 and are necessary
to design properly with the device. Especially for those not familiar with the ARM920T processor or
previous i.MX processor products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MX1 Product Brief (order number MC9328MX1P)
MC9328MX1 Reference Manual (order number MC9328MX1RM)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
Table 45. i.MX1 Data Sheet Revision History Rev. 7
Location
Revision
Signal Names and
Descriptions
Added the DMA_REQ signal to table.
Corrected signal name from USBD_OE to USBD_ROE
Corrected signal names
From: C10 BTRFGN, To: BTRFGND
From: G6 SIM_RST, To: SIM_RX
From: G7 UART2_TXD, To: SIM_CLK
Signal Multiplex Table i.MX1
Added Signal Multiplex table from Reference Manual with the following changes:
Changed I/O Supply Voltage, PB31–14, from NVDD3 to NVDD4
Corrected footnotes 1–5.
Changed AVDD2 references to QVDD, except for C14. Added footnote regarding ESD.
Changed occurrence of SD_SCLK to SD_CLK.
Removed 69K pull-up resistor from EB1, EB2, and added to D9
Changed first and second parameters descriptions:
From: Reference Clock freq range, To: DPLL input clock freq range
From: Double clock freq range, To: DPLL output freq range
Added Signal Multiplex table.
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