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参数资料
| 型号： | MC9328MX21DVK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 |
| 封装： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-289 |
| 文件页数： | 14/100页 |
| 文件大小： | 1979K |
| 代理商： | MC9328MX21DVK |
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MC9328MX21 Technical Data, Rev. 3.4
20
Freescale Semiconductor
Specifications
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
The DMA channel for which the DMA burst is ongoing has request source as external DMA
Request
(as per source select register setting).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present
in Table 13.
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External
DMA request is de-asserted immediately after sensing grant signal active.
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after
sensing grant signal active such that a new burst is not initiated.
Figure 5. Safe Maximum Timings for External Request De-Assertion
Ext_DMAReq
Ext_DMAGrant
tmin_assert
Ext_DMAReq
Data read from
External device
Data written to
External device
Ext_DMAGrant
tmax_write
tmax_read
tmax_req_assert
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:处理器 - 专门应用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21DVM | 功能描述:处理器 - 专门应用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21DVMR2 | 功能描述:处理器 - 专门应用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21S | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz |
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