- 您现在的位置：买卖IC网 > PDF目录45285 > MC9328MX21DVK (FREESCALE SEMICONDUCTOR INC) 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 PDF资料下载
参数资料
| 型号： | MC9328MX21DVK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 |
| 封装： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-289 |
| 文件页数： | 88/100页 |
| 文件大小： | 1979K |
| 代理商： | MC9328MX21DVK |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页当前第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
MC9328MX21 Technical Data, Rev. 3.4
88
Freescale Semiconductor
Specifications
3.20
DTACK Mode Memory Access Timing Diagrams
When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK
enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not
terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the
internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to
7.7
μs. Refer to the Section 3.5, “DPLL Timing Specifications” for more information on how to generate
different HCLK frequencies.
There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive
detection with a programmable insensitivity time. DTACK is only used during external asynchronous data
transfers, thus the SYNC bit in the chip select control registers must be cleared.
During edge detection mode, the EIM will terminate an external data transfer following the detection of
the DTACK signal’s rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection
mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode
can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following
bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register:
WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control
Register
AGE bit set in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements
of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the
rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal
32-bit access through an external 16-bit data port.
During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2
HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control
Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic
high, it will continue the data transfer at the programmed number of wait states. However, if the EIM
detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so
long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer
DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer.
Level detection is often used for asynchronous devices such graphic controller chips. Level detection may
be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip
select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select
Control Register and EIM Configuration Register:
EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register
BCD/DCT set to desired “insensitivity time” in the Chip Select Control Register. The “insensitivity
time” is dictated by the external device’s timing requirements.
AGE bit cleared in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements
of the external device.
The waveforms in the following section provide examples of the DTACK signal operation.
相关PDF资料 |
PDF描述 |
|---|---|
| MC9328MX21VH | 266 MHz, MICROPROCESSOR, PBGA289 |
| MC9328MX21CVG | 266 MHz, MICROPROCESSOR, PBGA289 |
| MC9328MX21CVH | 266 MHz, MICROPROCESSOR, PBGA289 |
| MC9328MX21DVH | 266 MHz, MICROPROCESSOR, PBGA289 |
| MC9328MX21DVG | 266 MHz, MICROPROCESSOR, PBGA289 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:处理器 - 专门应用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21DVM | 功能描述:处理器 - 专门应用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21DVMR2 | 功能描述:处理器 - 专门应用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21S | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz |
发布紧急采购，3分钟左右您将得到回复。