参数资料
型号: MC9S08QE32CLC
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
文件页数: 13/46页
文件大小: 985K
代理商: MC9S08QE32CLC
MC9S08QE32 Series MCU Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
20
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
8C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δf
dco_t
0.5
–1.0
±2
%fdco
9C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0
°C to 70 °C
Δf
dco_t
±0.5
±1
%fdco
10
C
FLL acquisition time3
tAcquire
——
1
ms
11
C
Long term jitter of DCO output clock (averaged over 2-ms
interval)4
CJitter
0.02
0.2
%fdco
1 Data in Typical column is characterized at 3.0 V, 25
°C or is typical recommended value.
2 The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
Table 12. Control Timing
Num
C
Rating
Symbol
Min
Typical1
Max
Unit
1D
Bus frequency (tcyc = 1/fBus)
VDD ≤ 2.1V
2.1<VDD ≤ 2.4V
VDD > 2.4Vs
fBus
DC
10
20
25.165
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
μs
3D
External reset pulse width2
textrst
100
ns
4
D
Reset low drive
trstdrv
34
× t
cyc
——
ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
μs
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5
× t
cyc
ns
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85
°C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
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