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Device User Guide — 9S12C32DGV1/D V01.01
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words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports. During external accesses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
The main difference between special modes and normal modes is that some of the bus control and system
control signals cannot be written in special modes.
4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
4.2.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to
the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.
All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance
inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.