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参数资料
| 型号： | MCAQE16GQAPR-MWA |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封装： | FBGA |
| 文件页数： | 38/65页 |
| 文件大小： | 799K |
| 代理商： | MCAQE16GQAPR-MWA |
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NAND Flash-based Solid State Disk
43
Sep. 27. 2006
5.8.1 Address
CS1
CS0
DA2
DA1
DA0
AN
A
N
A=asserted, N=negated
5.8.6 Field / bit description
Bits 7 through 3 are reserved.
SRST is the host software reset bit.
nIEN is the enable bit for the device Assertion of INTRQ to the host. When the nIEN bit is cleared to zero, and the device is
selected, INTRQ shall be enabled through a tri-state buffer and shall be asserted or negated by the device as appropriate. When the
nIEN bit is set to one, or the device is not selected, the INTRQ signal shall be in a high impedance state.
Bit 0 shall be cleared to zero.
76
5
4
3
2
1
0
rr
r
SRST
nIEN
0
5.8.2 Direction
This register is write only. If this address is read by the host, the Alternate Status register is read.
5.8.3 Access Restrictions
This register shall only be written when DMACK- is not asserted.
5.8.4 Effect
The content of this register shall take effect when written.
5.8.5 Functional description
This register allows a host to software reset attached devices and to enable or disable the assertion of the INTRQ signal by a
selected device. When the Device Control Register is written, both devices respond to the write regardless of which device is
selected. When the SRST bit is set to one, both devices shall perform the software reset protocol.
The device shall respond to the SRST bit when in the SLEEP mode.
5.8 Device Control Register
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