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参数资料
| 型号： | MCAQE16GQAPR-MWA |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封装： | FBGA |
| 文件页数： | 44/65页 |
| 文件大小： | 799K |
| 代理商： | MCAQE16GQAPR-MWA |
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NAND Flash-based Solid State Disk
49
Sep. 27. 2006
5.14 Status Register
5.14.1 Address
CS1
CS0
DA2
DA1
DA0
NA
A
A=asserted, N=negated
5.14.2 Direction
This register is read only. If this address is written to by the host, the Command register is written.
5.14.3 Access Restrictions
The contents of this register, except for BSY, shall be ignored when BSY is set to one. BSY is valid at all times. The contents of this
register are not valid while a device is in the Sleep mode.
5.14.4 Effect
Reading this register when an interrupt is pending causes the interrupt pending to be cleared. The host should not read the Status
Register when an interrupt is expected as this may clear the interrupt pending before the INTRQ can be recognized by the host.
5.14.6 Field / bit description
76
5
4
3
2
1
0
BSY
DRDY
#
DRQ
Obsolete
ERR
The register contains the device status. The contents of this register are updated to reflect the current state of the device and the
progress of any command being executed by the device.
5.14.5 Functional description
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