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参数资料
| 型号： | MCAQE16GQAPR-MWA |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封装： | FBGA |
| 文件页数： | 47/65页 |
| 文件大小： | 799K |
| 代理商： | MCAQE16GQAPR-MWA |
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NAND Flash-based Solid State Disk
51
Sep. 27. 2006
The DRDY bit shall be set to one by the device :
1) when the device is capable of accepting all commands for devices
When the DRDY bit is set to one :
1) the device shall accept and attempt to execute all implemented commands;
2) devices that implement the Power Management feature set shall maintain the DRDY bit set to one when they are in the Idle or
Standby modes.
5.14.6.3 Command dependent
The use of bits marked with # are command dependent. Bit 4 was formerly the DSC(Device Seek Complete) bit.
5.14.6.4 DRQ(Data request)
DRQ indicates that the device is ready to transfer a word of data between the host and the device. After the host has written the
Command Register the device shall either set the BSY bit to one or the DRQ bit to one, until command completion or the device has
performed a bus release for an overlapped command.
The DRQ bit shall be set to one by the device :
1) when BSY is set to one and data is ready for PIO transfer;
2) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one.
When the DRQ bit is set to one, the host may :
1) transfer data via PIO mode;
2) transfer data via DMA mode if DMARQ and DMACK- are asserted.
The DRQ bit shall be cleared to zero, the host may :
1) transfer data via DMA mode if DMARQ and DMACK- are asserted and BSY is set to one.
5.14.6.5 Obsolete bits
Some bits in this register were defined in previous ATA standards but have been declared obsolete in this spec
These bits are labeled "obsolete".
5.14.6.2 DRDY(Device ready)
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