参数资料
型号: MCF51JU32VFM
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 50 MHz, MICROCONTROLLER, QCC32
封装: 5 X 5 MM, QFN-32
文件页数: 41/72页
文件大小: 1031K
代理商: MCF51JU32VFM
Table 33. USB VREG electrical specifications
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
Run mode
Standby mode
3
TBD
3.3
2.8
3.6
V
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
TBD
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
100
ILIM
Short circuit current
TBD
290
TBD
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted, as well as
input signal transitions of 3 ns and a 50 pF maximum load on all SPI pins. All timing
assumes slew rate control is disabled and high drive strength is enabled for SPI output
pins.
Table 34. SPI master mode timing
Num.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBUS/2048
fBUS/2
Hz
fBUS is the
bus clock
as defined
2
tSPSCK
SPSCK period
2 x tBUS
2048 x
tBUS
ns
tBUS = 1/
fBUS
3
tLead
Enable lead time
1/2
tSPSCK
4
tLag
Enable lag time
1/2
tSPSCK
5
tWSPSCK
Clock (SPSCK) high or low time
tBUS - 30
1024 x
tBUS
ns
Table continues on the next page...
Communication interfaces
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
46
Preliminary
Freescale Semiconductor, Inc.
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MCF51QM128VFM FLASH, 50 MHz, MICROCONTROLLER, QCC32
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