参数资料
型号: MCF51QF32VHX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 50 MHz, MICROCONTROLLER, QCC64
封装: 9 X 9 MM, QFN-64
文件页数: 43/72页
文件大小: 1031K
代理商: MCF51QF32VHX
<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
2
6
7
MSB IN2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
MASTER LSB OUT
BIT 6 . . . 1
5
8
10
11
PORT DATA
(CPOL 0)
(CPOL 1)
PORT DATA
SS1
(OUTPUT)
3
10
11
4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
2
9
SPSCK
=
Figure 18. SPI master mode timing (CPHA=1)
Table 35. SPI slave mode timing
Num.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBUS/4
Hz
fBUS is the
bus clock
as defined
2
tSPSCK
SPSCK period
4 x tBUS
ns
tBUS = 1/
fBUS
3
tLead
Enable lead time
1
tBUS
4
tLag
Enable lag time
1
tBUS
5
tWSPSCK
Clock (SPSCK) high or low time
tBUS - 30
ns
6
tSU
Data setup time (inputs)
19.5
ns
7
tHI
Data hold time (inputs)
0
ns
8
ta
Slave access time
tBUS
ns
Time to
data active
from high-
impedanc
e state
9
tdis
Slave MISO disable time
tBUS
ns
Hold time
to high-
impedanc
e state
10
tv
Data valid (after SPSCK edge)
27
ns
11
tHO
Data hold time (outputs)
0
ns
Table continues on the next page...
Communication interfaces
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
48
Preliminary
Freescale Semiconductor, Inc.
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