
ColdFire Core
MOTOROLA
MCF5206 USERS MANUAL Rev 1.0
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If the access error occurs on an operand read, the processor immediately aborts the current
instructions execution and initiates exception processing. In this situation, any address
register updates attributable to the auto-addressing modes, {e.g., (An)+,-(An)}, has already
been performed. So, the programming model contains the updated An value. In addition, if
an access error occurs during the execution of a MOVEM instruction loading from memory,
any registers already updated before the fault occurs contains the operands from memory.
The ColdFire processor uses an imprecise reporting mechanism for access errors on write
operations. Since the actual write cycle may be decoupled from the processors issuing of
the operation, the signaling of an access error appears to be decoupled from the instruction
that generated the write. Accordingly, the PC contained in the exception stack frame merely
represents the location in the program when the access error was signaled, not when the
offending instruction was executed. All programming model updates associated with the
write instruction are completed. The NOP instruction can collect access errors for writes.
This instruction delays its execution until all previous operations to internal memory
resources, including all pending write operations, are complete. If any previous write
terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.5.2 Address Error Exception
Any attempted execution transferring control to an odd instruction address (i.e., if bit 0 of the
target address is set) results in an address error exception, vector number $3.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed
effective addressing mode generates an address error as does an attempted execution of a
full-format indexed addressing mode.
3.5.3 Illegal Instruction Exception
Any attempted execution of the $0000 and the $4AFC opwords generates an illegal
instruction exception, vector number $4. Additionally, any attempted execution of any line A
and most line F opcode generates their unique exception types, vector numbers 10 and 11,
respectively. ColdFire 5200 processors do not provide illegal instruction detection on the
extension words on any instruction, including MOVEC. If any other nonsupported opcode is
executed, the resulting operation is undefined.
3.5.4 Privilege Violation Exception
The attempted execution of a supervisor mode instruction while in user mode generates a
privilege violation exception, vector number $8. See the ColdFire Programmers Reference
Manual for lists of supervisor- and user-mode instructions.
3.5.5 Trace Exception
To aid in program development, the ColdFire 5200 processors provide an instruction-by-
instruction tracing capability. While in trace mode, indicated by the assertion of the T-bit in
the status register (SR[15] = 1), the completion of an instruction execution signals a trace
exception, vector number $9. This functionality allows a debugger to monitor program
execution.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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