参数资料
型号: MCF52256CAG66
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, ROHS COMPLIANT, LQFP-144
文件页数: 31/46页
文件大小: 560K
代理商: MCF52256CAG66
MCF52259 ColdFire Microcontroller, Rev. 4
Electrical Characteristics
Freescale Semiconductor
37
2.14
I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 13.
Table 24 lists specifications for the I2C output timing parameters shown in Figure 13.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
11
Start condition hold time
2
t
CYC
—ns
I2
Clock low period
8
t
CYC
—ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
1
ms
I6
Clock high time
4
t
CYC
—ns
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
t
CYC
—ns
I9
Stop condition setup time
2
t
CYC
—ns
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
111
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 24 are minimum values.
Start condition hold time
6
t
CYC
—ns
Clock low period
10
t
CYC
—ns
I32
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
Data hold time
7
t
CYC
—ns
I53
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
Clock high time
10
t
CYC
—ns
Data setup time
2
t
CYC
—ns
Start condition setup time (for repeated start
condition only)
20
t
CYC
—ns
Stop condition setup time
10
t
CYC
—ns
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