参数资料
型号: MCF5275LCVM133
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA196
封装: MAPBGA-196
文件页数: 15/44页
文件大小: 1242K
代理商: MCF5275LCVM133
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
22
8.5
Oscillator and Phase Lock Loop (PLLMRFM) Electrical
Specifications
4 The actual V
OH and VOL values for SSTL pads are dependent on the termination and drive strength used. The specifications
numbers assume no parallel termination.
5
Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
6
This parameter is characterized before qualification rather than 100% tested.
7
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination.
8
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
9
All functional non-supply pins are internally clamped to VSS and their respective VDD.
10 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
11 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not
present during the power-up sequence until the PLL has attained lock.
Table 11. PLL Electrical Specifications1
Characteristic
Symbol
Min
Max
Unit
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode (NOTE: fsys/2 = 2 × fref_1:1)
fref_crystal
fref_ext
fref_1:1
8
24
25
83
MHz
Core frequency
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
fcore
fsys/2
0
fref / 32
166
83
MHz
Loss of Reference Frequency 3, 5
fLOR
100
1000
kHz
Self Clocked Mode Frequency 4, 5
fSCM
TBD
MHz
Crystal Start-up Time 5, 6
tcst
—10
ms
EXTAL Input High Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VIHEXT
TBD
V
EXTAL Input Low Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VILEXT
TBD
V
XTAL Output High Voltage
IOH = 1.0 mA
VOH
TBD
V
XTAL Output Low Voltage
IOL = 1.0 mA
VOL
—TBD
V
XTAL Load Capacitance7
530
pF
PLL Lock Time 8
tlpll
750
s
Power-up To Lock Time 6, 9
With Crystal Reference
Without Crystal Reference10
tlplk
11
750
ms
s
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