参数资料
型号: MCF5327CVM240
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
封装: 15 X 15 MM, ROHS COMPLIANT, MAPBGA-196
文件页数: 13/50页
文件大小: 1114K
代理商: MCF5327CVM240
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
20
5.6
External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.
12
Crystal capacitive load
CL
See crystal
spec
13
Discrete load capacitance for XTAL
CL_XTAL
2*CL
CS_XTAL
CPCB_XTAL
7
pF
14
Discrete load capacitance for EXTAL
CL_EXTAL
2*CL–-
CS_EXTAL
CPCB_EXTAL
pF
17
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
10
TBD
% fsys/3
18
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
0.8
2.2
%fsys/3
19
VCO Frequency. fvco = (fref * PFD)/4
fvco
350
540
MHz
1 The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2 All internal registers retain data at 0 Hz.
3 This parameter is guaranteed by characterization before qualification rather than 100% tested.
4 Proper PC board layout procedures must be followed to achieve specifications.
5 This parameter is guaranteed by design rather than 100% tested.
6 This specification is the PLL lock time only and does not include oscillator start-up time.
7 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10
μs, or equivalently the modulation rate is 100 KHz.
11 Modulation range determined by hardware design.
Table 8. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF5327CVM240,
MCF53281CVM240,
MCF5328CVM240,
MCF5329CVM240
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