参数资料
型号: MCF5327CVM240
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
封装: 15 X 15 MM, ROHS COMPLIANT, MAPBGA-196
文件页数: 26/50页
文件大小: 1114K
代理商: MCF5327CVM240
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
32
Figure 18. Non-TFT Mode Panel Timing
Table 16. Sharp TFT Panel Timing
Num
Description
Minimum
Value
Unit
T1
LCD_SPL/LCD_SPR pulse width
1
Ts
T2
End of LCD_LD of line to beginning of LCD_HSYNC
1
HWAIT1+1
Ts
T3
End of LCD_HSYNC to beginning of LCD_LD of line
4
HWAIT2 + 4
Ts
T4
LCD_CLS rise delay from end of LCD_LD of line
3
CLS_RISE_DELAY+1
Ts
T5
LCD_CLS pulse width
1
CLS_HI_WIDTH+1
Ts
T6
LCD_PS rise delay from LCD_CLS negation
0
PS_RISE_DELAY
Ts
T7
LCD_REV toggle delay from last LCD_LD of line
1
REV_TOGGLE_DELAY+1
Ts
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.
Table 17. Non-TFT Mode Panel Timing
Num
Description
Minimum
Value
Unit
T1
LCD_HSYNC to LCD_VSYNC delay
2
HWAIT2 + 2
Tpix
T2
LCD_HSYNC pulse width
1
HWIDTH + 1
Tpix
T3
LCD_VSYNC to LCD_LSCLK
0
≤ T3 ≤ Ts
T4
LCD_LSCLK to LCD_HSYNC
1
HWAIT1 + 1
Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK
can be programmed as active high or active low. In Figure 18, all three signals are active high. When it is in CSTN
mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width
= 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
T1
T2
T4
T3
XMAX
LCD_VSYNC
LCD_LSCLK
LCD_HSYNC
LCD_LD[15:0]
T2
T1
Ts
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF5327CVM240,
MCF53281CVM240,
MCF5328CVM240,
MCF5329CVM240
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