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| 型号： | MCF5372LCVM240 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/46页 |
| 文件大小： | 0K |
| 描述： | IC MPU RISC 240MHZ 196-MAPBGA |
| 产品培训模块： | ColdFire® Embedded Voice Solution |
| 标准包装： | 126 |
| 系列： | MCF537x |
| 核心处理器： | Coldfire V3 |
| 芯体尺寸： | 32-位 |
| 速度： | 240MHz |
| 连通性： | EBI/EMI，以太网，I²C，SPI，SSI，UART/USART，USB，USB OTG |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 62 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.4 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 196-LBGA |
| 包装： | 托盘 |
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MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
18
5.6
External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
14
Discrete load capacitance for EXTAL
CL_EXTAL
2*CL–-
CS_EXTAL –
CPCB_EXTAL
pF
17
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
—
10
TBD
% fsys/3
18
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
0.8
2.2
%fsys/3
19
VCO Frequency. fvco = (fref * PFD)/4
fvco
350
540
MHz
1 The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2 All internal registers retain data at 0 Hz.
3 This parameter is guaranteed by characterization before qualification rather than 100% tested.
4 Proper PC board layout procedures must be followed to achieve specifications.
5 This parameter is guaranteed by design rather than 100% tested.
6 This specification is the PLL lock time only and does not include oscillator start-up time.
7 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10
μs, or equivalently the modulation rate is 100 KHz.
11 Modulation range determined by hardware design.
Table 8. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5372LCVM240J | 功能描述:32位微控制器 - MCU V3CORE RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MCF5373 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
| MCF5373_08 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
| MCF5373CAB180 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microprocessor Data Sheet |
| MCF5373L | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
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