参数资料
型号: MCHC11F1CFNE3
厂商: Freescale Semiconductor
文件页数: 72/158页
文件大小: 0K
描述: IC MCU 8BIT 1K RAM 68-PLCC
标准包装: 18
系列: HC11
核心处理器: HC11
芯体尺寸: 8-位
速度: 3MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 30
程序存储器类型: ROMless
EEPROM 大小: 512 x 8
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.75 V ~ 5.25 V
数据转换器: A/D 8x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
包装: 管件
PIN DESCRIPTIONS
MC68HC11F1
2-6
TECHNICAL DATA
2.8 MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes. Refer to SEC-
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that execution of an instruction has begun. The LIR pin is configured for
wired-OR operation (only pulls low). A series of E-clock cycles occurs during execution
of each instruction. The LIR signal is asserted (drives low) during the first E-clock cycle
of each instruction (opcode fetch). This output is provided for assistance in program
debugging.
The VSTBY pin is used to input RAM standby power. The MCU is powered from the
VDD signal unless the difference between the level of VSTBY and Vdd is greater than
one MOS threshold (about 0.7 volts). When these voltages differ by more than 0.7
volts, the internal 768-byte RAM and part of the reset logic are powered from VSTBY
rather than VDD. This allows RAM contents to be retained without VDD power applied
to the MCU. Reset must be driven low before VDD is removed and must remain low
until VDD has been restored to a valid level.
2.9 VRH and VRL
These pins provide the reference voltage for the analog-to-digital converter. Bypass
capacitors should be used to minimize noise on these signals. Any noise on VRH and
VRL will directly affect A/D accuracy.
2.10 R/W
In expanded and test modes, R/W indicates the direction of transfers on the external
data bus. A logic level one on this pin indicates that a read cycle is in progress. A logic
zero on this pin indicates that a write cycle is in progress and that no external device
should drive the data bus.
The E-clock can be used to enable external devices to drive data onto the data bus
during the second half of a read bus cycle (E clock high). R/W can then be used to
control the direction of data transfers. R/W drives low when data is being written to the
external data bus. R/W will remain low during consecutive data bus write cycles, such
as when a double-byte store occurs.
2.11 Port Signals
For the MC68HC11F1, 54 pins are arranged into six 8-bit ports: A, B, C, E, F, and G,
and one 6-bit port (D). Each of these seven ports serves a purpose other than I/O, de-
pending on the operating mode or peripheral functions selected. Note that ports B, C,
and F are available for I/O functions only in single-chip and bootstrap modes. The pins
of ports A, C, D, and G are fully bidirectional. Ports B and F are output-only ports. Port
E is an input-only port. Refer to Table 2-1 for details about the 54 port signals’ func-
tions within different operating modes.
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For More Information On This Product,
Go to: www.freescale.com
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