参数资料
型号: MCIMX27VJP4AR2
厂商: Freescale Semiconductor
文件页数: 71/152页
文件大小: 0K
描述: IC MPU IMX27 404TMAP
标准包装: 1,000
系列: i.MX27
核心处理器: ARM9
芯体尺寸: 32-位
速度: 400MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,LCD,POR,PWM,WDT
程序存储器类型: ROMless
RAM 容量: 45K x 8
电压 - 电源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振荡器型: 外部
工作温度: -20°C ~ 85°C
封装/外壳: 404-LFBGA
包装: 带卷 (TR)
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
25
Functional Description and Application Information
software configuration. The WDOG Timer module also generates a system reset via a software write to
the Watchdog Control Register (WCR) when there is a detection of a clock monitor event, an external
reset, an external JTAG reset signal, or if a power-on-reset has occurred.
2.3.38
Wireless External Interface Module (WEIM)
The Wireless External Interface Module (WEIM) handles the interface to devices external to the chip,
including generation of chip selects, clocks and controls for external peripherals and memory. It provides
asynchronous and synchronous access to devices with an SRAM-like interface.
The WEIM includes six chip selects for external devices, with two CS signals covering a range of
128 Mbytes, and the other four each covering a range of 32 Mbytes. The 128-Mbyte range can be
increased to 256 Mbytes when combined with the two signals. The WEIM offers selectable protection for
each chip select as well as programmable data port size. There is a programmable wait-state generator for
each chip select and support for Big Endian and Little Endian modes of operation per access.
2.3.39
Video Codec
The Video Codec module is the video processing module in the i.MX27 processor. It supports full duplex
video codec with 25 fps VGA resolution, supports multi-party calls, and integrates multiple video
processing standards, including H.264 BP, MPEG-4 SP, and H.263 P3 (including annex I, J, K, and T), D1
resolution, 30 fps—half-duplex.
NOTE
The Video Codec feature is not available on the i.MX27L
It has three 64-bit AHB-Lite master bus interfaces connecting to the EMI, which includes two read
channels and one write channel. Its 32-bit AHB-Lite master bus is connected to ARM Platform to access
system-internal SRAM.
The Video Codec module contains three major architectural components: video codec processing IP,
AXI-to-AHB bus protocol transfer module, and a 32-bit to 64-bit AHB master bus protocol transfer
module.
The Video Codec module supports following video stream processing features:
Multi-standard video codec
— MPEG-4 part-II simple profile encoding/decoding
— H.264/AVC baseline profile encoding/decoding
— H.263 P3 encoding/decoding
— Multi-party call: max processing four image/bitstream encoding and/or decoding
simultaneously
— Multi-format: for example, encodes MPEG-4 bitstream, and decodes H.264 bitstream
simultaneously
Coding tools
— High-performance motion estimation
– Single reference frame for both MPEG-4 and H.264 encoding
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