参数资料
型号: MCIMX27VJP4AR2
厂商: Freescale Semiconductor
文件页数: 87/152页
文件大小: 0K
描述: IC MPU IMX27 404TMAP
标准包装: 1,000
系列: i.MX27
核心处理器: ARM9
芯体尺寸: 32-位
速度: 400MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,LCD,POR,PWM,WDT
程序存储器类型: ROMless
RAM 容量: 45K x 8
电压 - 电源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振荡器型: 外部
工作温度: -20°C ~ 85°C
封装/外壳: 404-LFBGA
包装: 带卷 (TR)
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
4
Freescale Semiconductor
Functional Description and Application Information
1.3
Ordering Information
Table 1 provides ordering information for the MAPBGA, lead-free packages.
2
Functional Description and Application Information
2.1
ARM926 Microprocessor Core Platform
The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6
× 3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex.
The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master
Port 0.
The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.
Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the
MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB
is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL
memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred
to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the
user to trade off between high performance and high-code density. The ARM926EJ-S processor includes
features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time
(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and
provides a complete high-performance processor subsystem, including the following:
An ARM9EJ-S integer core
A Memory Management Unit (MMU)
Separate instruction and data AMBA AHB bus interfaces
ETM and JTAG-based debug support
Table 1. Ordering Information
Device
Temperature
Package
MCIMX27VOP4A
–20
° C to +85° C
1816-01
MCIMX27LVOP4A
–20
° C to +85° C
1816-01
MCIMX27MOP4A
–40
° C to +85° C
1931-04
MCIMX27LMOP4A
–40
° C to +85° C
1931-04
MCIMX27VJP4A
–20
° C to +85° C
1816-01
MCIMX27LVJP4A
–20
° C to +85° C
1816-01
MCIMX27MJP4A
–40
° C to +85° C
1931-04
MCIMX27LMJP4A
–40
° C to +85° C
1931-04
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