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| 型号： | MCIMX31CJMN4C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA473 |
| 封装： | 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-473 |
| 文件页数： | 16/108页 |
| 文件大小： | 2878K |
| 代理商： | MCIMX31CJMN4C |
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Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
15
4.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any MCIMX31C board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
may result in any or all of the following situations:
Cause excessive current during power-up phase
Prevent the device from booting
Cause irreversible damage to the MCIMX31C (worst-case scenario)
4.2.1
Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power-up sequence. Power-up
logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of
NOTE
Stages need to be performed in the order shown; however, within each stage,
supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1,
and NVCC3 through NVCC10 do not need to be powered up in the order shown.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Figure 2. Option 1 Power-Up Sequence for Silicon Revision 2.0 and 2.0.1
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
Hold POR Asserted
1, 3
Notes:
1
The board design must guarantee that supplies reach 90% level before
transition to the next state, using Power Management IC or other
means.
2
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until
IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are
no restrictions.
3
The parallel paths in the flow indicate that supply group NVCC2,
NVCC21, and NVCC22, and supply group FVCC, MVCC, SVCC, and
UVCC ramp-ups are independent.
4
FUSE_VDD should not be driven on power-up for Silicon Revision 2.0
and 2.0.1. This supply is dedicated for fuse burning (programming),
and should not be driven upon boot-up.
5
Raising IOQVDD before NVCC21 produces a slight increase in current
drain on IOQVDD of approximately 3–5 mA. The current increase will
not damage the IC. Refer to Errata ID TLSbo91750 for details.
FVCC, MVCC, SVCC, UVCC
1,3
4
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX31CVMN4D,
MCIMX31LCVMN4D,
MCIMX31CVMN4C,
MCIMX31LCVMN4C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCIMX31CJMN4C | 制造商:Freescale Semiconductor 功能描述:IC 32BIT MPU 400MHZ MAPBGA-473 |
| MCIMX31CJMN4CR2 | 功能描述:处理器 - 专门应用 TORTOLA MX31 AUTO FULL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31CJMN4D | 功能描述:处理器 - 专门应用 MX31 2.0.1 AUTO FULL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31CJMN4DR2 | 功能描述:处理器 - 专门应用 MX31 2.0.1 AUTO FULL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31CVKN5C | 功能描述:IC MPU MAP I.MX31 457-MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX31 标准包装:1 系列:AVR® ATmega 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，SPI，UART/USART 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:32 程序存储器容量:32KB（16K x 16） 程序存储器类型:闪存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:44-TQFP 包装:剪切带 (CT) 其它名称:ATMEGA324P-B15AZCT |
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