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| 型号： | MCIMX31LCVMN4C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA473 |
| 封装： | 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-473 |
| 文件页数： | 13/108页 |
| 文件大小： | 2878K |
| 代理商： | MCIMX31LCVMN4C |
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MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
12
Freescale Semiconductor
Electrical Characteristics
Table 7 provides the operating ranges.
NOTE
The term NVCC in this section refers to the associated supply rail of an
input or output. The association is shown in the Signal Multiplexing chapter
of the reference manual.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Table 7. Operating Ranges
Symbol
Parameter
Min
Max
Units
QVCC,
QVCC1,
QVCC4
Core Operating Voltage1,2
1 Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively).
2 The core voltage must be higher than 1.38V to avoid corrupted data during transfers from the USB HS. Please refer to Errata
file ENGcm02610 ID
V
0
≤ fARM ≤ 400 MHz
1.22
1.47
State Retention Voltage3
3 The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC)
is operational in State Retention (SR) mode.
0.95
—
NVCC1,
NVCC3–10
I/O Supply Voltage, except DDR4
4 Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the
duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
1.75
3.1
V
NVCC2,
NVCC21,
NVCC22
I/O Supply Voltage, DDR only
1.75
1.95
V
FVCC, MVCC,
SVCC, UVCC
PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage5
5 PLL voltage must not be altered after power-up, otherwise the PLL will be unstable and lose lock. To minimize inducing noise
on the PLL supply line, source the voltage from a low-noise, dedicated supply. PLL parameters in Table 28, "DPLL
Specifications," on page 31, are guaranteed over the entire specified voltage range.
1.3
1.47
V
IOQVDD
On-device Level Shifter Supply Voltage
1.6
1.9
V
FUSE_VDD
Fusebox read Supply Voltage6
6 In read mode, FUSE_VDD can be floated or grounded.
——
V
Fusebox write (program) Supply Voltage7
7 Fuses might be inadvertently blown if written to while the voltage is below this minimum.
3.0
3.3
V
TA
Operating Ambient Temperature Range
–40
85
oC
Tj
Operating Junction Temperature Range
—
105
oC
Table 8. Specific Operating Ranges for Silicon Revision 2.0 and 2.0.1
Symbol
Parameter
Min
Max
Units
FUSE_VDD
Fusebox read Supply Voltage1
——
V
Fusebox write (program) Supply Voltage2
3.0
3.3
V
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX31CVMN4D,
MCIMX31LCVMN4D,
MCIMX31CVMN4C,
MCIMX31LCVMN4C
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