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参数资料
| 型号： | MCM64E918 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步迟写快速静态RAM) |
| 中文描述： | 晚8分位同步静态随机存储器写入速度（800万位同步迟写快速静态内存） |
| 文件页数： | 12/24页 |
| 文件大小： | 503K |
| 代理商： | MCM64E918 |
MCM64E918
MCM64E836
12
MOTOROLA FAST SRAM
FUNCTIONAL DESCRIPTION
USING DESELECT
Function control pins B1:B2 set to 1:0 will be latched on a
rising edge of the input clock (CK), and launch a deselect at
the next CK clock (pipelined). Deselect puts the data bus into
a high–impedance state. Deselect can be used to avoid bus
contention by putting the data bus into a high–impedance
state before performing a write. The sequence for switching
from a read to a write should be: READ, DESELECT,
WRITE.
COHERENCY
This part is fully coherent. This means that when a write is
performed at an address, and a read of that same address
follows immediately, the data just written is read back.
BURSTING
Function control pins are used to select single or double
reads and writes. When a double read or write is selected,
the data is managed on both the rising and falling edges of
the echo clock, which is the double data rate feature of this
FSRAM. All burst sequences are determined with the LBO
pin per the Burst Sequence table.
Function control pins B1:B2 set to 1:1 increments the
address and continues the previous function. This com-
bination of B1:B2 can immediately follow any of the other
read or write functions. As long as the B1:B2 pins are set to
1:1 on rising edges of the input clock, a continuous read or
write from sequential addresses can be performed without
having to resupply the address (refer to the Bus Cycle State
diagram and Three–Wire Synchronous Function Control
table).
READS/WRITES
The DDR latches address and control lines on the rising
edge of the input (CK) clock.
Single reads are selected by setting function control lines
B1:B2:B3 = 0:1:1. This functionality resembles the non–burst
read timing of a pipelined BurstRAM (pre–DDR). Only 1 byte
of data will result from each address and control clocked into
the part. Data changes only on the rising edge of the clock.
Double reads are selected by setting B1:B2:B3 = 0:1:0.
This will cause a burst of two, but at twice the input clock
rate. Data is available after the rising and the falling clock
edges of the output clock (refer to the Double and Single
Read Timing diagram).
Single writes have late write functionality. Single writes are
selected with B1:B2:B3 = 0:0:1. Data In must meet setup and
hold times with respect to the rising edge of the input
clock, CK.
Double writes are also late writes. Double writes are
selected with B1:B2:B3 = 0:0:0. The data rate is twice the
applied clock in a double write, so Data In must meet setup
and hold times with respect to the rising and falling edges
of the input clock, CK.
ECHO CLOCK
This part is equipped with an echo clock. The echo clock is
an output clock that aids in the synchronization of data. After
power up, the echo clock is free running. The data that is out-
put during a read cycle is referenced to the echo clock out-
puts.
STARTUP CONDITIONS/STOP CLOCK
Power up conditions are expected to vary from application
to application. Echo clocks (CQ and CQ) are not pipelined,
and will respond to the input clock (CK) immediately. One
way to design for this situation is to power up and start the
DDR, run until all signals are transitioning smoothly, and then
stop the clock and start it again, using the echo clock edges
after the stop clock and not before the stop clock. This will
allow for synchronization of the echo clock. The stop clock
can be used anywhere as long as the minimum and maxi-
mum clock pulse specifications are not violated.
OUTPUT IMPEDANCE CIRCUITRY
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, a 250
resistor will give an out-
put impedance of 50
.
Impedance updates occur during write and deselect
cycles.
The actual change in the impedance occurs in small incre-
ments and is binary. The binary impedance has 256 values
and therefore, there are no significant disturbances that
occur on the output because of this smooth update method.
At power up, the output impedance will take up to 65,000
cycles for the impedance to be completely updated.
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