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参数资料
| 型号： | MCM64E918 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步迟写快速静态RAM) |
| 中文描述： | 晚8分位同步静态随机存储器写入速度（800万位同步迟写快速静态内存） |
| 文件页数： | 21/24页 |
| 文件大小： | 503K |
| 代理商： | MCM64E918 |
MCM64E918
MCM64E836
21
MOTOROLA FAST SRAM
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state.
NOT IEEE 1149.1 COMPLIANT.
IDCODE
001**
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function.
NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
Places bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state.
*Instruction codes expressed in binary; MSB on left, LSB on right.
**Default instruction automatically loaded at power–up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary; MSB on left, LSB on right.
CAPTURE–DR
EXIT1–DR
EXIT2–DR
UPDATE–DR
CAPTURE–IR
EXIT1–IR
EXIT2–IR
UPDATE–IR
SHIFT–IR
PAUSE–IR
SHIFT–DR
PAUSE–DR
TEST–LOGIC
RESET
0
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 6. TAP Controller State Diagram
0
1
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