参数资料
型号: MCP14E5-E/P
厂商: Microchip Technology
文件页数: 12/26页
文件大小: 0K
描述: IC MOSFET DVR 4.0A DUAL 8DIP
标准包装: 60
配置: 低端
输入类型: 反相和非反相
延迟时间: 46ns
电流 - 峰: 4A
配置数: 2
输出数: 2
电源电压: 4.5 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
MCP14E3/MCP14E4/MCP14E5
4.0
4.1
APPLICATION INFORMATION
General Information
MOSFET drivers are high-speed, high current devices
V DD = 18V
which are intended to source/sink high peak currents to
charge/discharge the gate capacitance of external
MOSFETs or IGBTs. In high frequency switching power
supplies, the PWM controller may not have the drive
capability to directly drive the power MOSFET. A MOS-
Input
1 μF
0.1 μF
Ceramic
Output
FET driver like the MCP14E3/MCP14E4/MCP14E5
family can be used to provide additional source/sink
current capability.
An additional degree of control has been added to the
MCP14E3/MCP14E4/MCP14E5 family. There are
separate enable functions for each driver that allow for
the immediate termination of the output pulse
Input
MCP14E4
(1/2 MCP14E5)
C L = 2200 pF
regardless of the state of the input signal.
+5V
90%
4.2
MOSFET Driver Timing
Input
The ability of a MOSFET driver to transition from a fully
0V
10%
off state to a fully on state are characterized by the
drivers rise time (t R ), fall time (t F ), and propagation
delays (t D1 and t D2 ). The MCP14E3/MCP14E4/
MCP14E5 family of drivers can typically charge and
18V
Output
0V
t D1 90%
10%
t R
t D2
90%
10%
t F
discharge a 2200 pF load capacitance in 15 ns along
with a typical matched propagation delay of 50 ns.
Figure 4-1 and Figure 4-2 show the test circuit and
timing waveform used to verify the MCP14E3/
FIGURE 4-2:
Waveform.
Non-Inverting Driver Timing
MCP14E4/MCP14E5 timing.
4.3
Enable Function
V DD = 18V
The ENB_A and ENB_B enable pins allow for indepen-
dent control of OUT A and OUT B respectively. They
Input
Input
+5V
Input
1 μF
MCP14E3
(1/2 MCP14E5)
0.1 μF
Ceramic
Output
C L = 2200 pF
90%
are active high and are internally pulled up to V DD so
that the default state is to enable the driver. These pins
can be left floating for normal operation.
When an enable pin voltage is above the enable pin
high threshold voltage, V EN_H (2.4V typical), that driver
output is enabled and allowed to react to changes in
the INPUT pin voltage state. Likewise, when the enable
pin voltage falls below the enable pin low threshold
voltage, V EN_L (2.0V typical), that driver output is dis-
abled and does not respond the changes in the INPUT
pin voltage state. When the driver is disabled, the out-
put goes to a low state. Refer to Table 4-1 for enable
pin logic. The threshold voltages of the enable function
are compatible with logic levels. Hysteresis is provided
to help increase the noise immunity of the enable
0V
18V
Output
10%
t D1
90%
t F
t D2
t R
90%
function, avoiding false triggers of the enable signal
during driver switching. For robust designs, it is
recommended that the slew rate of the enable pin
signal be greater than 1 V/ns.
0V
10%
10%
There are propagation delays associated with the
driver receiving an enable signal and the output
FIGURE 4-1:
Waveform.
DS22062B-page 12
Inverting Driver Timing
reacting. These propagation delays, t D3 and t D4 , are
graphically represented in Figure 4-3 .
? 2008 Microchip Technology Inc.
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