参数资料
型号: MCP1754ST-1802E/CB
厂商: Microchip Technology
文件页数: 16/42页
文件大小: 0K
描述: IC REG LDO 1.8V .15A SOT-23A-3
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 1.8V
输入电压: 3.6 V ~ 16 V
电压 - 压降(标准): 0.3V @ 150mA
稳压器数量: 1
电流 - 输出: 150mA(最小)
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: TO-236-3,SC-59,SOT-23-3
供应商设备封装: SOT-23A-3
包装: 标准包装
其它名称: MCP1754ST-1802E/CBDKR
MCP1754/MCP1754S
3.4
Shutdown Input (SHDN)
3.6
Exposed Pad (EP)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state.
Some of the packages have an exposed metal pad on
the bottom of the package. The exposed metal pad
gives the device better thermal characteristics by
providing a good thermal path to either the PCB or heat
sink to remove heat from the device. The exposed pad
of the package is internally connected to GND.
3.5
Power Good Output (PWRGD)
For fixed applications, the PWRGD output is an open-
drain output used to indicate when the LDO output
voltage is within 92% (typically) of its nominal
regulation value. The PWRGD threshold has a typical
hysteresis value of 2%. The PWRGD output is delayed
by 100 μs (typical) from the time the LDO output is
within 92% + 2% (typical hysteresis) of the regulated
output value on power-up. This delay time is internally
fixed. The PWRGD pin may be pulled up to V IN or
V OUT . Pulling up to V OUT conserves power when the
device is in shutdown (/SHDN = 0V) mode.
DS22276A-page 16
? 2011 Microchip Technology Inc.
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