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| 型号： | MCP2050T-330E/SL |
| 厂商： | Microchip Technology |
| 文件页数： | 3/42页 |
| 文件大小： | 0K |
| 描述： | IC TXRX LIN 3.3V LDO 14-SOIC |
| 产品培训模块： | Microchip MCP20xx LIN Transceiver Overview |
| 标准包装： | 2,600 |
| 系列： | * |
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2012 Microchip Technology Inc.
DS22299B-page 11
MCP2050
1.4.3
TXD/LBUS TIME-OUT TIMER
LIN bus can be driven to a dominant level either from
TXD pin or externally. An internal timer deactivates the
LBUS transmitter if a dominant status (LOW) on LIN bus
lasts longer than Bus Dominant Time-out Time tTO(LIN)
(approximately 20 ms); at the same time, RXD output
is put in recessive (HIGH), FAULT/TXE is also driven to
LOW and the internal LIN pull-up resistor is discon-
nected. The timer is reset on any recessive LBUS status
or POR mode. The recessive status on LBUS can be
caused either by the bus being externally pulled up or
by TXD pin being returned high.
1.5
Internal Voltage Regulator
The MCP2050 has a positive regulator capable of
supplying +5.00 or +3.30 VDC ±3% at up to 70 mA of
load current over the entire operating temperature
range of -40°C to +125°C. The regulator uses an LDO
design, is short-circuit-protected and will turn the
regulator output off if its output falls below the
Shutdown Voltage Threshold VSD.
With a load current of 70 mA, the minimum input to
output voltage differential required for the output to
remain in regulation is typically +0.5V (+1V maximum
over the full operating temperature range). Quiescent
current is less than 100 A with a full 70 mA load
current when the input to output voltage differential is
greater than +3.00V.
Regarding the correlation between VBB, VREG and IDD,
refer to Figure 1-11 and Figure 1-12. When the input
voltage (VBB) drops below the differential needed to
provide stable regulation, the voltage regulator output
VREG will track the input down to approximately VOFF.
The regulator will turn off the output at this point. This
will allow PIC microcontrollers, with internal POR cir-
cuits, to generate a clean arming of the Power-on
Reset trip point. The MCP2050 will then monitor VBB
and turn on the regulator when VBB is above the thresh-
old of regulator turn on voltage VON.
Under specific ambient temperature and battery volt-
age range, the voltage regulator can output as high as
150 mA current.
For current load capability of the voltage regulator, refer
to Figure 1-11 and Figure 1-11.
In Power-down mode, the VBB monitor is turned off.
The regulator requires an external output bypass
capacitor for stability. See FIGURE 2-1: “ESR Curves
For Load Capacitor Selection” for correct capacity
and ESR for stable operation.
FIGURE 1-8:
VOLTAGE REGULATOR BLOCK DIAGRAM
Note:
The regulator overload current limit is
approximately 250 mA. The regulator
output voltage VREG is monitored. If output
voltage VREG is lower than VSD, the
voltage regulator will turn off. After a
recovery time of about 3 ms, the VREG will
be checked again. If there is no short
circuit, (VREG > VSD) then the voltage
regulator remains on.
Pass
Element
Sampling
Network
Buffer
VREG
VBB
VSS
Fast
Transient
Loop
VREF
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