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| 型号： | MCP2050T-330E/SL |
| 厂商： | Microchip Technology |
| 文件页数： | 38/42页 |
| 文件大小： | 0K |
| 描述： | IC TXRX LIN 3.3V LDO 14-SOIC |
| 产品培训模块： | Microchip MCP20xx LIN Transceiver Overview |
| 标准包装： | 2,600 |
| 系列： | * |
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2012 Microchip Technology Inc.
DS22299B-page 5
MCP2050
1.2
WINDOWED WATCHDOG RESET
The Watchdog Timer monitors for activity on the
Windowed
Watchdog
Timer
Trigger
input
pin
WWDTTRIG. The WWDTTRIG pin is expected to be
strobed within a given time frame. When this time
frame has expired, without an edge transition on the
WWDTTRIG pin, the WWDTRESET pin is driven active
(LOW) to reset the system. This feature is enabled by
connecting a resistor between the WWDTSELECT pin
and VSS. Monitoring is then done by requiring the host
processor to force an falling edge transition on the
WWDTTRIG pin within a predetermined time frame
(TWD).
The start time of the trigger window is fixed at 50% of
the total watchdog period, after the last trigger. The
length of the window is determined by the value of the
resistor on pin WWDTSELECT. The Watchdog Timer is
disabled if WWDTSELECT is floating.
1.2.1
WWDT During Initial Power-up
The WWDTRESET is driven high after a power-on
reset. The Watchdog Timer begins counting at this
point, awaiting an edge on WWDTTRIG pin. Note that
there is no window enabled, yet. If no falling edge is
detected on the WWDTTRIG pin before the timer
expires, the WWDTRESET is pulse low and the timer
is restarted. When a trigger edge on the WWDTTRIG
pin is seen, the window is enabled and the timer is reset.
FIGURE 1-2:
WWDTRESET DURING INITIAL POWER-UP
POWER-UP” shows the behavior of the WWDTRE-
SET pin after a system reset with no trig at all. If no trig
is given during the power-up window, WWDTRESET is
reset low for the time tWDRST.
The power-up window length tPOWERUP duration is
determined by the value of the resistor connected
between pin WWDTSELECT and pin VSS, while the
reset pulse duration is about 150 us.
Duration for tPOWERUP and tWDRST are:
tPOWERUP = 0.8 ms x (RWWDTSELECT+1) +/- 15%
tWDRST = 150us +/- 35%
RWWDTSELECT is in k
Once a trig is asserted, the power-up sequence “stops”
and the normal behavior begins.
1.2.2
WINDOWED WATCHDOG
BEHAVIOR
After windowed watchdog begins its normal behavior,
three different cases can appear.
A pulse (falling edge) on the WWDTTRIG pin is
detected within the trigger window; the watchdog
timer will be reset, and a new watchdog period will
begin;WWDTRESETpinremainshigh(Figure 1-3.)
A pulse (falling edge) on the WWDTTRIG pin is
detected before the trigger window (too early trig-
ger); WWDTRESET is asserted (LOW) immedi-
ately after the falling edge is detected for
approximately tWDRST; the counter is reset and the
next watchdog period begins at the rising edge of
the voltage on WWDTRESET pin (Figure 1-14).
No pulse on the WWDTTRIG pin is detected dur-
ing the whole watchdog window (no trigger),
WWDTRESET is asserted (LOW) for approxi-
mately tWDRST when the timer has expired; the
counter is reset and the next watchdog period
begins at the rising edge of the voltage on
WWDTRESET pin (Figure 1-5).
The trigger window is between 50% to 100% of the
watchdog window length. The window length is
determined
by
the
external
resistor
between
WWDTSELECT pin and VSS.
WINDOW LENGTH = 0.2 ms x (RWWDTSELECT + 1)+/
-15%.
tWDRST = 150uS+/-35%
RWWDTSELECT is in k
; its value ranges from 33 k to
680 k
and window length ranges from 6.8 ms to 136+/
-15%.
If the WWDTSELECT pin is floating, the watchdog is
disabled and the WWDTRESET remains HIGH.
tPOWERUP
tWDRST
tPOWERUP
Internal
reset
WWDTRESET
tPOWERUP
tWDRST
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