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| 型号： | MCP3304T-CI/SL |
| 厂商： | Microchip Technology |
| 文件页数： | 20/48页 |
| 文件大小： | 0K |
| 描述： | IC ADC 13BIT 2.7V 4CH SPI 16SOIC |
| 标准包装： | 2,600 |
| 位数： | 13 |
| 采样率（每秒）： | 100k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极 |
| 其它名称： | MCP3304TCI/SL |
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2011 Microchip Technology Inc.
DS21697F-page 27
MCP3302/04
6.3
Using the MCP3302/04 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the
rising edge. Because communication with the
MCP3302 and MCP3304 devices may not need
multiples of eight clocks, it will be necessary to provide
more clocks than are required. This is usually done by
sending ‘leading zeros’ before the start bit. For
example, Figure 6-4 and Figure 6-5 show how the
MCP3302/04 devices can be interfaced to a MCU with
a hardware SPI port. Figure 6-4 depicts the operation
shown in SPI Mode 0,0, which requires that the SCLK
from the MCU idles in the ‘low’ state, while Figure 6-5
shows the similar case of SPI Mode 1,1, where the
clock idles in the ‘high’ state.
As shown in Figure 6-4, the first byte transmitted to the
A/D Converter contains 6 leading zeros before the start
bit. Arranging the leading zeros this way produces the
13 data bits to fall in positions easily manipulated by the
MCU. The sign bit is clocked out of the A/D Converter
on the falling edge of clock number 11, followed by the
remaining data bits (MSB first). After the second eight
clocks have been sent to the device, the MCU receive
buffer will contain 2 unknown bits (the output is at high-
impedance for the first two clocks), the null bit, the sign
bit, and the 4 highest order bits of the conversion. After
the third byte has been sent to the device, the receive
register will contain the lowest order eight bits of the
conversion results. Easier manipulation of the
converted data can be obtained by using this method.
Figure 6-5 shows the same situation in SPI Mode 1,1,
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
FIGURE 6-4:
SPI Communication with the MCP3302/04 using 8-bit segments
(Mode 0,0: SCLK idles low).
12
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
DIN
X = Don’t Care Bits
17
18
19
20
21
22
23
24
DOUT
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3 B2
B1
B0
HI-Z
MCU latches data from A/D Converter
Data is clocked out of
A/D Converter on falling edges
on rising edges of SCLK
Don’t Care
SGL/
DIFF
D0
D1
Start
00
0
1X
X
XXX
DO
XX
X
XXXXX
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
0
??????
??
D1
D2
SGL/
DIFF
Start
Bit
(Null)
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X
Data stored into MCU receive
register after transmission of first 8
bits
Data stored into MCU receive
register after transmission of
second 8 bits
Data stored into MCU receive
register after transmission of last
8 bits
X
SB
D2
? = Unknown Bits
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