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| 型号： | MCP40D19T-503E/LT |
| 厂商： | Microchip Technology |
| 文件页数： | 27/43页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 50K 128TAPS SC70-5 |
| 标准包装： | 1 |
| 接片： | 128 |
| 电阻（欧姆）： | 50k |
| 电路数： | 1 |
| 温度系数： | 标准值 150 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP（5 引线），SC-88A，SOT-353 |
| 供应商设备封装： | SC-70-5 |
| 包装： | 标准包装 |
| 产品目录页面： | 674 (CN2011-ZH PDF) |
| 其它名称： | MCP40D19T-503E/LTDKR |
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2009 Microchip Technology Inc.
DS22152B-page 33
MCP40D17/18/19
5.0
SERIAL INTERFACE -
I2C MODULE
A 2-wire I2C serial protocol is used to write or read the
digital potentiometer’s wiper register. The I2C protocol
utilizes the SCL input pin and SDA input/output pin.
The I2C serial interface supports the following features:
Slave mode of operation
7-bit addressing
The following clock rate modes are supported:
- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s
Support Multi-Master Applications
The serial clock is generated by the Master.
The I2C Module is compatible with the Phillips I2C
specification. Philips only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
for the MCP40D17, MCP40D18, and MCP40D19
devices are defined in this section of the data sheet.
FIGURE 5-1:
Typical Application I2C Bus
Configurations.
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
5.1
I2C I/O Considerations
I2C specifications require active low, passive high
functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to VSS (common) with a pull-up resistor. The
specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts
the
pull-up
value
for
optimum
system
performance.
Common pull-up values range from 1 k
Ω to a maximum
of ~10 k
Ω. Power sensitive applications tend to choose
higher values to minimize current losses during
communication but these applications also typically
utilize lower VDD.
The SDA and SCL float (are not driving) when the
device is powered down.
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.
5.1.1
SLOPE CONTROL
The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
Single I2C Bus Configuration
Host
Controller
Device 1
Device 3
Device n
Device 2
Device 4
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