参数资料
型号: MCP41050T-I/SN
厂商: Microchip Technology
文件页数: 12/28页
文件大小: 0K
描述: IC POT DIGITAL 50K 1CH SPI 8SOIC
标准包装: 3,300
接片: 256
电阻(欧姆): 50k
电路数: 1
温度系数: 标准值 800 ppm/°C
存储器类型: 易失
接口: 3 线串行(芯片选择)
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
MCP41XXX/42XXX
DS11195C-page 2
2003 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS: 10 k
VERSION
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Rheostat Mode
Nominal Resistance
R
8
10
12
k
TA = +25°C (Note 1)
Rheostat Differential Non Linearity
R-DNL
-1
±1/4
+1
LSB
Rheostat Integral Non Linearity
R-INL
-1
±1/4
+1
LSB
Rheostat Tempco
RAB/T
800
ppm/°C
Wiper Resistance
RW
52
100
VDD = 5.5V, IW = 1 mA, code 00h
RW
73
125
VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current
IW
-1
+1
mA
Nominal Resistance Match
R/R
0.2
1
%
MCP42010 only, P0 to P1; TA = +25°C
Potentiometer Divider
Resolution
N
8
Bits
Monotonicity
N
8
Bits
Differential Non-Linearity
DNL
-1
±1/4
+1
LSB
Integral Non-Linearity
INL
-1
±1/4
+1
LSB
Voltage Divider Tempco
VW/T
1
ppm/°C Code 80h
Full Scale Error
VWFSE
-2
-0.7
0
LSB
Code FFh, VDD = 5V, see Figure 2-25
VWFSE
-2
-0.7
0
LSB
Code FFh, VDD = 3V, see Figure 2-25
Zero Scale Error
VWZSE
0
+0.7
+2
LSB
Code 00h, VDD = 5V, see Figure 2-25
VWZSE
0
+0.7
+2
LSB
Code 00h, VDD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range
VA,B,W
0—
VDD
Capacitance (CA or CB)
15
pF
f = 1 MHz, Code = 80h, see Figure 2-30
Capacitance
C
W
5.6
pF
f = 1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use VDD = 5V)
Bandwidth -3dB
BW
1
MHz
VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time
tS
—2
S
VA = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage
eNWB
—9
nV/
√Hz VA = Open, Code 80h, f =1 kHz
Crosstalk
CT
—-95
—dB
VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation
Schmitt Trigger High-Level Input Voltage
VIH
0.7VDD
——
V
Schmitt Trigger Low-Level Input Voltage
VIL
0.3VDD
V
Hysteresis of Schmitt Trigger Inputs
VHYS
—0.05VDD
Low-Level Output Voltage
VOL
0.40
V
IOL = 2.1 mA, VDD = 5V
High-Level Output Voltage
VOH
VDD - 0.5
V
IOH = -400 A, VDD = 5V
Input Leakage Current
ILI
-1
+1
A
CS = VDD, VIN = VSS or VDD, includes VA SHDN=0
Pin Capacitance (All inputs/outputs)
CIN, COUT
—10
pF
VDD = 5.0V, TA = +25°C, fc = 1 MHz
Power Requirements
Operating Voltage Range
VDD
2.7
5.5
V
Supply Current, Active
IDDA
340
500
A
VDD = 5.5V, CS = VSS, fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static
IDDS
—0.01
1
A
CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity
PSS
0.0015
0.0035
%/%
VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h
PSS
0.0015
0.0035
%/%
VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h
Note
1:
VAB = VDD, no connection on wiper.
2:
Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50 A for
VDD = 3V and IW = 400 A for VDD = 5V for 10 k version. See Figure 2-26 for test circuit.
3:
INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4:
Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
5:
Measured at VW pin where the voltage on the adjacent VW pin is swinging full-scale.
6:
Supply current is independent of current through the potentiometers.
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