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参数资料
| 型号： | MCP41050T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC POT DIGITAL 50K 1CH SPI 8SOIC |
| 标准包装： | 3,300 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 1 |
| 温度系数： | 标准值 800 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 3 线串行（芯片选择） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
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2003 Microchip Technology Inc.
DS11195C-page 5
MCP41XXX/42XXX
Absolute Maximum Ratings
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V
Storage temperature .....................................-60°C to +150°C
Ambient temp. with power applied ................-60°C to +125°C
ESD protection on all pins
..................................................≥ 2kV
Notice: Stresses above those listed under “maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Clock Frequency
FCLK
——
10
MHz
Clock High Time
tHI
40
—
ns
Clock Low Time
tLO
40
—
ns
CS Fall to First Rising CLK Edge
tCSSR
40
—
ns
Data Input Setup Time
tSU
40
—
ns
Data Input Hold Time
tHD
10
—
ns
SCK Fall to SO Valid Propagation Delay
tDO
—80
ns
SCK Rise to CS Rise Hold Time
tCHS
30
—
ns
SCK Rise to CS Fall Delay
tCS0
10
—
ns
CS Rise to CLK Rise Hold
tCS1
100
—
ns
CS High Time
tCSH
40
—
ns
Reset Pulse Width
tRS
150
—
ns
RS Rising to CS Falling Delay Time
tRSCS
150
—
ns
CS rising to RS or SHDN falling delay time
tSE
40
—
ns
CS low time
tCSL
100
—
ns
Shutdown Pulse Width
tSH
150
—
ns
Note
1:
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI =
40 ns, tDO = 80 ns and tSU = 40 ns.
2:
Applies only to the MCP42XXX devices.
3:
Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
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