参数资料
型号: ADSP-21479KBCZ-2A
厂商: Analog Devices Inc
文件页数: 19/72页
文件大小: 0K
描述: IC DSP SHARC 266MHZ LP 196CSPBGA
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
时钟速率: 266MHz
非易失内存: ROM(4Mb)
芯片上RAM: 5Mb
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 196-LFBGA,CSPBGA
供应商设备封装: 196-CSPBGA(12x12)
包装: 托盘
Rev. A
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Page 26 of 72
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September 2011
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 10. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 8 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Reset
Figure 8. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF
Y1
R1
1MΩ *
XTAL
CLKIN
C2
22pF
16.67
R2
47Ω *
ADSP-2147x
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Table 20. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST
1
RESET Pulse Width Low
4 × tck
ns
tSRST
RESET Setup Before CLKIN Low
8
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100
μs while RESET is low, assuming stable
Vdd and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
tSRST
tWRST
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