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参数资料
| 型号： | ADSP-21479KBCZ-2A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 196CSPBGA |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA，CSPBGA |
| 供应商设备封装： | 196-CSPBGA（12x12） |
| 包装： | 托盘 |
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Rev. A
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Page 12 of 72
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September 2011
The watch dog timer also has an internal RC oscillator that can
be used as the clock source. The internal RC oscillator can be
used as an optional alternative to using an external clock applied
to the WDT_CLIN pin.
Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the SHARC
processor. Connect RTC pins RTXI and RTXO with external
components as shown in Figure 3.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low power state. The RTC provides several pro-
grammable interrupt options, including interrupt per second,
minute, hour, or day clock ticks, interrupt on programmable
stopwatch countdown, or interrupt at a programmed alarm
time. An RTCLKOUT signal that operates at 1 Hz is also pro-
vided for calibration.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter. When the alarm
interrupt is enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value in
the alarm control register. There are two alarms: The first alarm
is for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch inter-
rupt is enabled and the counter underflows, an interrupt is
generated.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory boots at system power-up from an 8-bit
EPROM via the external port, an SPI master, or an SPI slave.
Booting is determined by the boot configuration
(BOOT_CFG2–0) pins in Table 9.
A running reset feature is used to reset the processor core and
peripherals without resetting the PLL and SDRAM controller,
or performing a boot. The functionality of the RESETOUT
/RUNRSTIN pin has now been extended to also act as the input
for initiating a running reset. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
Power Supplies
The processors have separate power supply connections for the
internal (VDD_INT) and external (VDD_EXT), power supplies. The
internal and analog supplies must meet the VDD_INT specifica-
tions. The external supply must meet the VDD_EXT specification.
All external supply pins must be connected to the same power
supply.
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDD_INT and GND.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processors to mon-
itor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators pro-
vides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor's JTAG interface ensures that the emulator will not
affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The processors are supported with a complete set of CROSS-
CORE
software and hardware development tools, including
Analog Devices emulators and VisualDSP++
development
environment. The same emulator hardware that supports other
SHARC processors also fully emulates the processors.
EZ-KIT Lite Evaluation Board
For evaluation of the processors, use the EZ-KIT Lite
board
being developed by Analog Devices. The board comes with on-
chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
Figure 3. External Components for RTC
RTXO
C1
C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
RTXI
R1
Table 9. Boot Mode Selection
BOOT_CFG2–0
1
Booting Mode
000
SPI Slave Boot
001
SPI Master Boot (from Flash and Other Slaves)
010
AMI User Boot (for 8-bit Flash Boot)
011
No Boot (Processor Executes from Internal
ROM After Reset)
100
Reserved
1xx
Reserved
1 The BOOT_CFG2 pin is not available on the 100-lead package.
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