参数资料
| 型号： | MCP4728-E/UN |
| 厂商： | Microchip Technology |
| 文件页数： | 22/33页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT W/I2C 10-MSOP |
| 视频文件： | MCP4728 Evaluation Board Demo |
| 标准包装： | 100 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | EEPROM，I²C，串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，单极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 673 (CN2011-ZH PDF) |
| 配用： | MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728 |
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2010 Microchip Technology Inc.
DS22187E-page 29
MCP4728
5.0
I2C SERIAL INTERFACE
COMMUNICATIONS
The MCP4728 device uses a two-wire I2C serial
interface. When the device is connected to the I2C bus
line, the device works as a slave device. The device
supports standard, fast and high speed modes.
The following sections describe how to communicate
with the MCP4728 device using the I2C serial interface
commands.
5.1
Overview of I2C Serial Interface
Communications
An example of the hardware connection diagram is
shown in Figure 7-1. A device that sends data onto the
bus is defined as the transmitter, and a device receiving
data, as the receiver. The bus has to be controlled by a
master (MCU) device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions. Both master (MCU) and
slave (MCP4728) can operate as transmitter or
receiver, but the master device determines which mode
is activated.
Communication is initiated by the master (MCU) which
sends the START bit, followed by the slave (MCP4728)
address byte. The first byte transmitted is always the
slave (MCP4728) address byte, which contains the
device code (1100), the address bits (A2, A1, A0), and
the R/W bit. The device code for the MCP4728 device
is 1100, and the address bits are user-writable.
When the MCP4728 device receives a Read command
(R/W = 1), it transmits the contents of the DAC input
registers and EEPROM sequentially. When writing to
the device (R/W = 0), the device will expect Write
command type bits in the following byte. The reading
and various writing commands are explained in the
following sections.
The MCP4728 device supports all three I2C serial
communication operating modes:
Standard Mode: bit rates up to 100 kbit/s
Fast Mode: bit rates up to 400 kbit/s
High Speed Mode (HS mode): bit rates up to
3.4 Mbit/s
Refer to the Philips I2C document for more details of
the I2C specifications.
5.1.1
HIGH-SPEED (HS) MODE
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by sending a special
address byte of 00001XXX following the START bit.
The XXX bits are unique to the high-speed mode
Master. This byte is referred to as the high-speed
Master Mode Code (HSMMC). The MCP4728 device
does not acknowledge this byte. However, upon
receiving this command, the device switches to HS
mode and can communicate at up to 3.4 Mbit/s on SDA
and SCL lines. The device will switch out of the HS
mode on the next STOP condition.
For more information on the HS mode, or other I2C
modes, please refer to the Philips I2C specification.
5.2
I2C BUS CHARACTERISTICS
The specification of the I2C serial communication
defines the following bus protocol:
Data transfer may be initiated only when the bus
is not busy
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined using Figure 5-1.
5.2.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
5.2.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line, while the
clock (SCL) is HIGH, determines a START condition.
All commands must be preceded by a START
condition.
5.2.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line, while the
clock (SCL) is HIGH, determines a STOP condition. All
operations must be ended with a STOP condition.
5.2.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
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