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参数资料
| 型号： | MCP4728EV |
| 厂商： | Microchip Technology |
| 文件页数： | 29/33页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 12BIT 4CH DAC MCP4728 |
| 视频文件： | MCP4728 Evaluation Board Demo |
| 标准包装： | 1 |
| DAC 的数量： | 4 |
| 位数： | 12 |
| 数据接口： | I²C |
| 设置时间： | 6µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | MCP4728 |
| 产品目录页面： | 673 (CN2011-ZH PDF) |
| 相关产品： | MCP4728T-E/UN-ND - IC DAC 12BIT W/I2C 10-MSOP MCP4728-E/UN-ND - IC DAC 12BIT W/I2C 10-MSOP |
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2010 Microchip Technology Inc.
DS22187E-page 5
MCP4728
Analog Output (Output Amplifier)
Output Voltage Swing
VOUT
—
FSR
—
V
Full Scale Range
FSR
—
VDD
—V
VREF =VDD
FSR = from 0.0V to VDD
—VREF
—V
VREF = Internal, Gx =1,
FSR = from 0.0 V to VREF
—2 * VREF
—V
VREF = Internal, Gx =2,
FSR = from 0.0V to 2 * VREF
Output Voltage
Settling Time
TSETTLING
—6
—
s
Analog Output Time Delay
from Power-Down Mode
TdExPD
—4.5
—
s
VDD =5V,
Time delay to settle to new
reference
TdREF
—
26
—
s
From External to Internal
Reference
—
44
—
s
From Internal to External
Reference
Power Supply Rejection
PSRR
—
-57
—
dB
VDD =5V±10%, VREF = Internal
Capacitive Load Stability
CL
—
1000
pF
RL =5 kΩ
No oscillation,
Slew Rate
SR
—
0.55
—
V/s
Phase Margin
pM
—
66
—
Degree
(°)
CL =400 pF, RL = ∞
Short Circuit Current
ISC
—15
24
mA
VDD =5V,
All VOUT Pins = Grounded.
Tested at room temperature.
Short Circuit Current
Duration
TSC_DUR
—
Infinite
—
hours
DC Output Impedance
ROUT
—1
—
Ω
Normal mode
—1
—
k
Ω
Power-Down mode 1
(PD1:PD0 = 0:1), VOUT to VSS
—100
—
k
Ω
Power-Down mode 2
(PD1:PD0 = 1:0), VOUT to VSS
—500
—
k
Ω
Power-Down mode 3
(PD1:PD0 = 1:1), VOUT to VSS
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at V
DD = +2.7V to 5.5V, VSS =0V,
RL =5 kΩ, CL = 100 pF, GX =1, TA = -40°C to +125°C. Typical values are at +25°C, VIH =VDD, VIL =VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Note 1:
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
2:
The power-up ramp rate measures the rise of VDD over time.
3:
This parameter is ensured by design and not 100% tested.
4:
This parameter is ensured by characterization and not 100% tested.
5:
Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6:
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7:
This parameter is indirectly tested by Offset and Gain error testing.
8:
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9:
This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.
This time delay is not included in the output settling time specification.
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