参数资料
型号: MCZ33937EKR2
厂商: Freescale Semiconductor
文件页数: 16/48页
文件大小: 0K
描述: IC PRE-DRIVER 3PHASE 54-SOIC
标准包装: 1,000
系列: SMARTMOS™
配置: 3 相桥
输入类型: 非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 15V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 带卷 (TR)
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ? V PWR = V SUP ? 40 V, -40 ? C ? T A ? 135 ? C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING
Maximum Frequency of SPI Operation
f OP
4.0
MHz
Internal Time Base
Internal Time Base drift from value at 25 ? C (52)
f TB
TC TB
13
-5.0
17
25
5.0
MHz
%
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
(52)
(52)
t LEAD
t LAG
100
100
ns
ns
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
(52)
(52)
t SISU
t SIHOLD
25
25
ns
ns
SI, CS, SCLK Signal Rise Time
(52) , (53)
t RSI
5.0
ns
SI, CS, SCLK Signal Fall Time (52) , (53)
Time from Falling Edge of CS to SO Low-impedance (52) , (54)
Time from Rising Edge of CS to SO High-impedance (52) , (55)
t FSI
t SOEN
t SODIS
5.0
55
100
100
125
ns
ns
ns
Time from Rising Edge of SCLK to SO Data Valid
(52) , (56)
t VALID
80
125
ns
Time from Rising Edge of CS to Falling Edge of the next CS
(52)
t DT
200
ns
Notes
52.
53.
54.
55.
56.
This parameter is guaranteed by design, not production tested.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
TIMING DIAGRAMS
CS
0.2 V DD
t L EA D
t
t LAG
t SISU t SIHOLD
SCLK
0 .7 V D D
0 .2 V D D
DI(HO LD)
SI
0 .7 V D D
0 .2 V D D
MSB i n
t DO(E N)
t SOEN
t V A LI D
t (DIS )
t DO SODIS
SO
0 .7 V D D
0 .2 V D D
MSB out
LSB out
Figure 4. SPI Interface Timing
33937A
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
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